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(R)
X80000, X80001
Data Sheet March 18, 2005 FN8148.0
Smart Power PlugTM Penta-Power Sequence Controller with Hot Swap
The X80000 contains three major functions: a power communications controller, a power sequencing controller, and a hotswap controller. The power communications controller allows smart power supply control via the backplane using the SMBus protocol. The system can check for voltage, current, and manufacturing ID compliance before board insertion. The power distribution network can monitor the status of the negative voltage supply, DC voltage supplies, and hardshort events by accessing the Fault Detection Register and General Purpose EEPROM of the device. Each device has a unique slave address for identification. The power sequencer controller time sequences up to five DC-DC modules. The X80000 allows for various hardwired configurations, either parallel or relay sequencing modes. The power good, enable and voltage good signals provide for flexible DC-DC timing configurations. Each voltage enable signal has a programmable delay. In addition, the voltage good signals can be monitored remotely via the fault detection register (thru the SMBus). The hot swap controller allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. The X80000 family of devices offers a modular, power distribution approach by providing flexibility to solve the hotswap and power sequencing issues for insertion, operations, and extraction. Hardshort Detection and Retry with Delay, Noise filtering, Insertion Overcurrent Bypass, and Gate Current selection are some of the programmable features of the device. During insertion, the gate of an external power MOSFET is clamped low to suppress contact bounce. The undervoltage/overvoltage circuits and the power on reset circuitry suppress the gate turn on until the mechanical bounce has ended. The X80000 turns on the gate with a user set slew rate to limit the inrush current and incorporates an electronic circuit breaker set by a sense resistor. After the load is successfully charged, the PWRGD signal is asserted; indicating that the device is ready to power sequence the DC-DC power bricks.
Features
* Integrates Three Major Functions - Smart Power Plug communications - Programmable power sequencing - Programmable Hot Swap controller * Smart Power PlugTM - Intelligent board insertion allows verification of board and power supply resources prior to system insertion. - Fault detection register records the cause of the faults - Soft extraction - Soft re-insertion - Remote gate shutdown/turn on - Power ID/manufacturing ID memory (2kb of EEPROM) * Programmable Power Sequencing - Sequence up to 5 DC/DC converters. - Four independent voltage enable pins - Four programmable time delay circuits - Soft Power Sequencing - restart sequence without power cycling. * Hot Swap Controller - Programmable overvoltage and undervoltage protection - Undervoltage lockout for battery/redundant supplies - Programmable slew rate for external FET gate control - Electronic circuit breaker - overcurrent detection and gate shut-off - Programmable overcurrent limit during Insertion - Programmable hardshort retry with retry failure flag - Typically operates from -30V to -80V. Tolerates transients to -200V (limited by external components) * Available Packages - 32-lead Quad No-Lead Frame (QFN)
Applications
* -48V Hot Swap Power Backplane/Distribution Central Office, Ethernet for VOIP * Card Insertion Detection * Power Sequencing DC-DC/Power Bricks * IP Phone Applications * Databus Power Interfacing * Custom Industrial Power Backplanes * Distributed Power Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X80000, X80001 Pinout
X80000, X80001 (7X7 QFN) TOP VIEW
BATT-ON PWRGD
Ordering Information
PART NUMBER X80000Q32I OV 74.9 68.0 UV1 42.4 42.4 UV2 33.2 33.2 TEMP RANGE I I PKG 32 Ld QFN 32 Ld QFN PART MARK 80000I 80001I
MRH
IGQ0
IGQ1
FAR
NC VEE
X80001Q32I
VRGO A0 V4GOOD EN4 V3GOOD EN3 V2GOOD EN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (7mm x 7mm) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC MRC WP RESET V1GOOD EN1 SCL SDA
GATE
DRAIN
VDD
VEE
Typical Application
BackPlane DC-DC Module 1 ON/OFF DC-DC Module 2 ON/OFF
VUV/OV
SENSE
NC
A1
X80000 X80001 SCL SDA Insert Control -48V RTN R5 30K 1% R4 182K 1% VUV/OV OV=71V UV=37V VDD R6 10K 1% EN1 EN2 EN3 OptoIsolation SCL SDA MRH PWRGD V1GOOD V2GOOD V3GOOD
DC-DC Module 3 ON/OFF
DC-DC Module 4 ON/OFF
V1 V2
V3
VEE SENSE GATE DRAIN 12V 4.7V Rs -48V 0.02 5% Q1 IRFR120 0.1F 100 4.7K 3.3n
100K
V4
2
FN8148.0 March 18, 2005
X80000, X80001
Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . -65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on given pin (Hot Side Functions): Vov/uv pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE SENSE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mV + VEE VEE pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -80V DRAIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48V + VEE PWRGD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + VEE GATE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + VEE FAR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + VEE MRH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE BATT_ON pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE Voltage on given pin (Cold Side Functions): ENi pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ViGOOD pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE SDA, SCL, WP, A0, A1 pins . . . . . . . . . . . . . . . . . . . . .5.5V + VEE MRC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE IGQ1 and IGQ0 pins . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V + VEE D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300C
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40C to 85C Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Specifications
SYMBOL DC CHARACTERISTICS VDD IDD VRGO IRGO IGATE
Standard Settings
Over the recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Operating Range Supply Current Regulated 5V output VRGO current output Gate Pin Current Gate Drive On, VGATE = VEE, VSENSE = VEE (sourcing) VGATE - VEE = 3V VSENSE-VEE = 0.1V (sinking) IRGO = 10A
10
12 2.5
14 5 5.5 50
V mA
4.5
A A
46.2
52.5
58.8
9 VDD-0.01 0.9 VEE + 4 1 VDD 1.1 VEE + 5 VEE + 2
mA V V V V A A
VGATE VPGA VIHB VILB ILI ILO
External Gate Drive (Slew Rate Control) Power Good Threshold (PWRGD High to Low) Voltage Input High (BATT_ON) Voltage Input Low (BATT_ON) Input Leakage Current (MRH, MRC) Output Leakage Current (V1GOOD, V2GOOD, V3GOOD, V4GOOD, RESET) Input LOW Voltage (MRH, MRC, IGQ0, IGQ1) Input HIGH Voltage (MRH, MRC, IGQ0, IGQ1)
IGATE = 50A Referenced to VEE VUV1 < VUV/OV < VOV
VIL = GND to VCC All ENi = VRGO for i = 1 to 4
10 10
VIL VIH
-0.5 + VEE (VEE + 5) x 0.7
(VEE + 5) x 0.3 (VEE + 5) + 0.5
V V
3
FN8148.0 March 18, 2005
X80000, X80001
Electrical Specifications
SYMBOL VOL Standard Settings
Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER Output LOW Voltage (RESET, V1GOOD, V2GOOD, V3GOOD, V4GOOD, FAR, PWRGD) Output Capacitance (RESET, V1GOOD, V2GOOD, V3GOOD, V4GOOD, FAR) TEST CONDITIONS IOL = 4.0mA MIN TYP MAX VEE + 0.4 UNIT V
COUT (Note 1)
VOUT = 0V
8
pF
CIN (Note 1) Input Capacitance (MRH, MRC) VOC VOCI Overcurrent threshold Overcurrent threshold (Insertion)
VIN = 0V VOC = VSENSE - VEE VOC = VSENSE - VEE PWRGD = HIGH Initial Power Up condition 45 135 50 150
6 55 165
pF mV mV
VOVR
Overvoltage threshold (rising) X80000 Referenced to VEE X80001 3.85 3.49 3.90 3.54 3.95 3.59 V V
VOVF
Overvoltage threshold (falling) X80000 Referenced to VEE X80001 3.82 3.46 Referenced to VEE BATT-ON = VEE Referenced to VEE BATT-ON = VRGO Referenced to VEE Referenced to VEE Referenced to VEE Referenced to VEE Referenced to VEE Referenced to VEE 2.19 2.16 1.71 1.68 0.9 1.2 3.87 3.51 2.24 2.21 1.76 1.73 1 1.3 VRGO / 2 3.92 3.56 2.29 2.26 1.81 1.78 1.1 1.4 V V V V V V V V V V V V
VUV1R VUV1F VUV2R VUV2F VDRAINF VDRAINR VTRIP1 (Note 1) VTRIP2 (Note 1) VTRIP3 (Note 1) VTRIP4 (Note 1)
Undervoltage 1 threshold (rising) Undervoltage 1 threshold (falling) Undervoltage 2 threshold (rising) Undervoltage 2 threshold (falling) Drain sense voltage threshold (falling) Drain sense voltage threshold (rising) EN1 Trip Point Voltage EN2 Trip Point Voltage EN3 Trip Point Voltage EN4 Trip Point Voltage
AC CHARACTERISTICS tFOC tFUV tFOV tVFR tBATT_ON tMRC tMRH tMRCE tMRCD tMRHE Sense High to Gate Low Under Voltage conditions to Gate Low Overvoltage Conditions to Gate Low Overvoltage/undervoltage failure recovery time to VDD does not drop below 3V, No Gate =1V. other failure conditions. Delay BATT_ON Valid Minimum time high for reset valid on the MRC pin Minimum time high for reset valid on the MRH pin Delay from MRC enable to PWRGD HIGH Delay from MRC disable to PWRGD LOW Delay from MRH enable to Gate Pin LOW No Load Gate is On, No Load IGATE = 60A, No Load 5 5 1.0 200 1.0 1.6 1.6 400 2.4 1.5 0.5 1.0 1.2 2.5 1 1.5 1.6 100 3.5 1.5 2 2 s s s s ns s s s ns s
4
FN8148.0 March 18, 2005
X80000, X80001
Electrical Specifications
SYMBOL tMRHD tRESET_E tQC Standard Settings
Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER Delay from MRH disable to GATE reaching 1V Delay from PWRGD or ViGOOD to RESET valid LOW Delay from IGQ1 and IGQ0 to valid Gate pin current TSC1 = 0; TSC0 = 0 TF1 = 0; TF0 = 1 90 4.5 45 TPOR1 = 0; TPOR0 = 0 90 100 5 50 100 50 Gate = VDD Gate = VDD Drain = VEE Drain = VEE 1 1 1 1 TEST CONDITIONS IGATE = 60A, No Load MIN 1.8 TYP MAX 2.6 1 1 110 5.5 55 110 UNIT s s s ms s ms ms ns s s s s
tSC_RETRY Delay between retries tNF tDPOR tSPOR tTO tPDHLPG (Note 1) tPDLHPG (Note 1) tPGHLPG (Note 1) tPGLHPG (Note 1) NOTE: 1. This parameter is based on characterization data. Noise Filter for Overcurrent Device Delay before Gate assertion Delay after PWRGD and all ViGOOD signals are active before RESET assertion ViGOOD turn off time Delay from Drain good to PWRGD LOW Delay from Drain fail to PWRGD HIGH Delay from Gate good to PWRGD LOW Delay from Gate fail to PWRGD HIGH
Equivalent A.C. Output Load Circuit
5V 5V 5V
4.6k RESET FAR PWRGD 30pF
4.6k V1GOOD, V2GOOD, V3GOOD, 30pF V4GOOD,
4.6k
SDA
30pF
A.C. Test Conditions
Input pulse levels Input rise and fall times Input and output timing levels Output load VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Standard output load
5
FN8148.0 March 18, 2005
X80000, X80001
VTH tDPOR VDD VOV VUV VUV/OV tFOV tVFR tFUV tVFR
MRH
VOCI VOC
SENSE
GATE
1V
1V
FIGURE 1. OVERVOLTAGE/UNDERVOLTAGE GATE TIMING
VTH tDPOR VDD VOCI VOC SENSE tFOC tSC_RETRY
Always Retry VUV < VUV/OV < VOV MRH = HIGH
tSC_RETRY
GATE
tFOC
FIGURE 2. OVERCURRENT GATE TIMING
Initial Power-up VDD
VTRIPi ENi tTO ViGOOD tDELAYi Enable DC/DC supply tTO
i = 1, 2, 3, 4
FIGURE 3. ViGOOD TIMINGS
6
FN8148.0 March 18, 2005
X80000, X80001
tMRH MRC tMRC
MRH
GATE
1V
PWRGD tMRHD tMRCE tMRCD
tMRHE
FIGURE 4. MANUAL RESET (HOT SIDE) MRH
FIGURE 5. MANUAL RESET (COLD SIDE) MRC
tDHLPG VDRAIN tDLHPG VGATE tGLHPG PWRGD tGHLPG
ENi
V1GOOD
tDELAY1
V2GOOD
tDELAY2
V3GOOD
tDELAY3
V4GOOD
tDELAY4
RESET
tSPOR
PWRGD or
tRESET_E
any ENi LOW to HIGH (1st occurance)
FIGURE 6. PWRGD AND RESET TIMINGS
7
FN8148.0 March 18, 2005
X80000, X80001
Electrical Specifications
SYMBOL Programmable Parameters
Over the recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
DC CHARACTERISTICS VCB IGATE Over Current Trip Voltage Range (VCB = VSENSE - VEE) Gate Pin Pull-Up Current. (error) (current) Factory Setting is 50mV (see VOCI). For other options, contact Intersil. Gate Drive On; VGATE = VEE, IGQ1=0; IGQ0=0 9.2 10.5 21.0 31.5 42.0 46.2 52.5 63.0 64.7 73.5 84.0 94.5 105.0 115.5 126.0 136.5 147.0 138.6 157.5 168.0 9.2 64.7 138.6 10.57 73.5 157.5 400 11.8 82.3 176.4 176.4 82.3 58.5 11.8 A A A A A A A A A A A A A A A A A A A mV 30 -12 100 12 mV %
IG3 = 0; IG2= 0; IG1 = 0; IG0 = 0 Factory Default IG3 = 0; IG2= 0; IG1 = 0; IG0 = 1 IG3 = 0; IG2= 0; IG1 = 1; IG0 = 0 IG3 = 0; IG2= 0; IG1 = 1; IG0 = 1 IG3 = 0; IG2= 1; IG1 = 0; IG0 = 0 IG3 = 0; IG2= 1; IG1 = 0; IG0 = 1 IG3 = 0; IG2= 1; IG1 = 1; IG0 = 0 IG3 = 0; IG2= 1; IG1 = 1; IG0 = 1 IG3 = 1; IG2= 0; IG1 = 0; IG0 = 0 IG3 = 1; IG2= 0; IG1 = 0; IG0 = 1 IG3 = 1; IG2= 0; IG1 = 1; IG0 = 0 IG3 = 1; IG2= 0; IG1 = 1; IG0 = 1 IG3 = 1; IG2= 1; IG1 = 0; IG0 = 0 IG3 = 1; IG2= 1; IG1 = 0; IG0 = 1 IG3 = 1; IG2= 1; IG1 = 1; IG0 = 0 IG3 = 1; IG2= 1; IG1 = 1; IG0 = 1 IG3-IG0 = Don't Care IGQ1=0; IGQ0=1 IG3-IG0 = Don't Care IGQ1=1; IGQ0=0 IG3-IG0 = Don't Care IGQ1=1; IGQ0=1 VPGA VOCI Power Good Threshold Accuracy Over current threshold (Insertion) VS1 = 0 VS1 = 0 VS1 = 1 VS1 = 1 VS0 = 0 VS0 = 1 VS0 = 0 VS0 = 1 VDRAIN - VEE, High to Low Transition. Default Factory Setting is 47V. Referenced to VEE PWRGD = HIGH Factory Default
45 90 135 180
50 100 150 200
55 110 165 220
mV mV mV mV
AC CHARACTERISTICS tSC_RETRY Delay between Retries TSC1 = 0 TSC1 = 0 TSC1 = 1 TSC1 = 1 TSC0 = 0 TSC0 = 1 TSC0 = 0 TSC0 = 1 Factory Default 90 450 0.9 4.5 100 500 1 5 110 550 1.1 5.5 ms ms s s
8
FN8148.0 March 18, 2005
X80000, X80001
Electrical Specifications
SYMBOL tNF Programmable Parameters
Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER Noise Filter for Overcurrents F1 = 0 F1 = 0 F1 = 1 F1 = 1 tSPOR F0 = 0 F0 = 1 F0 = 0 F0 = 1 Factory Default 90 450 0.9 4.5 Factory Default 90 450 0.9 4.5 100 500 1 5 110 550 1.1 5.5 ms ms s s 100 500 1 5 110 550 1.1 5.5 ms ms s s 4.5 9 18 TEST CONDITIONS Factory Default 0 5 10 20 5.5 11 22 s s s s MIN. TYP. MAX. UNIT
Delay before RESET assertion TPOR1 = 0 TPOR1 = 0 TPOR1 = 1 TPOR1 = 1 TPOR0 = 0 TPOR0 = 1 TPOR0 = 0 TPOR0 = 1
tDELAYi
Time Delay used in Power Sequencing (i = 1 to 4) TiD1 = 0 TiD1 = 0 TiD1 = 1 TiD1 = 1 TiD0 = 0 TiD0 = 1 TiD0 = 0 TiD0 = 1
Serial Interface
Over the recommended operating conditions unless otherwise specified. SYMBOL DC CHARACTERISTICS ICC1 (Note 1) ICC2 (Note 1) ILI ILO Active Supply Current (VDD) Read to Memory or CRs Active Supply Current (VDD) Write to Memory or CRs Input Leakage Current (SCL, WP, A0, A1) Output Leakage Current (SDA) VIL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz 2.5 3.0 10 10 -0.5 + VEE (VEE + 5) x 0.7 (VEE + 5) x 0.3 (VEE + 5) + 0.5 mA mA A A V V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIL = GND to VCC VSDA = GND to VCC Device is in Standby (Note 2)
VIL (Note 3) Input LOW Voltage (SDA, SCL, WP, A0, A1) VIH (Note 3) Input HIGH Voltage (SDA, SCL, WP, A0, A1) VHYS Schmitt Trigger Input Hysteresis Fixed input level VCC related level VOL Output LOW Voltage (SDA) IOL = 4.0mA (2.7-5.5V) IOL = 2.0mA (2.4-3.6V)
VEE + 0.2 .05 x (VEE + 5) VEE + 0.4
V V V
AC CHARACTERISTICS fSCL tIN tAA SCL Clock Frequency Pulse width Suppression Time at inputs SCL LOW to SDA Data Out Valid 50 0.1 1.5 400 kHz ns s
9
FN8148.0 March 18, 2005
X80000, X80001
Serial Interface (Continued)
Over the recommended operating conditions unless otherwise specified. SYMBOL tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF tSU:WP tHD:WP Cb PARAMETER Time the bus is free before start of new transmission Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time WP Setup Time WP Hold Time Capacitive load for each bus line 5 TEST CONDITIONS MIN 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 20 +.1Cb (Note 1) 20 +.1Cb (Note 1) 0.6 0 400 10 300 300 TYP MAX UNIT s s s s s ns s s ns ns ns s s pF ms
tWC (Note 2) EEPROM Write Cycle Time NOTE:
2. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Timing Diagrams
tBUF tF tHIGH tLOW tR tBUF SCL tSU:STA tHD:STA SDA IN tAA SDA OUT tDH tHD:DAT tSU:DAT tHD:DAT tSU:STO tHD:STO
FIGURE 7. BUS TIMING
10
FN8148.0 March 18, 2005
X80000, X80001
START SCL
Clk 1 Slave Address Byte
Clk 9
SDA IN tSU:WP WP tHD:WP
FIGURE 8. WP PIN TIMING
SCL
SDA
8th Bit of Last Byte
ACK tWC Stop Condition Start Condition
FIGURE 9. WRITE CYCLE TIMING
Symbol Table
WAVEFORM INPUTS
Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed
OUTPUTS
Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known
11
FN8148.0 March 18, 2005
X80000, X80001 Typical Performance Characteristics
52.000 UNDERVOLTAGE 2 THRESHOLD (V) INRUSH CURRENT LIMIT (mV) 51.000 50.000 49.000 48.000 47.000 46.000 -55 -40 -25 -10 1.780 1.770 1.760 1.750 1.740 1.730 1.720 1.710 1.700 1.690 -55 -40 -25 -10 5 20 35 50 65 TEMPERATURE 80 95 110 125 FALLING RISING
5
20
35
50
65
80
95 110 12
TEMPERATURE
FIGURE 10. OVERCURRENT THRESHOLD vs TEMPERATURE
FIGURE 11. UNDERVOLTAGE 1 THRESHOLD vs TEMPERATURE
3.92 3.91 3.90 3.89 3.88 3.87 3.86 3.85 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE FALLING RISING ENi THRESHOLD (V) OV THRESHOLD (V)
2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 2.475 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 12. OVERVOLTAGE THRESHOLD vs TEMPERATURE
FIGURE 13. ENi THRESHOLD vs TEMPERATURE
UNDERVOLTAGE 1 THRESHOLD (V)
2.250 2.240 2.230 RISING 2.220 2.210 2.200 2.190 -55 -40 -25 -10 FALLING GATE CURRENT (A)
200 150A 160
120 70A 50A 40 10A
80
5
20 35 50 65 TEMPERATURE
80
95 110 125
0 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 14. UNDERVOLTAGE 1 THRESHOLD vs TEMPERATURE
FIGURE 15. IGATE (SOURCE) vs TEMPERATURE
12
FN8148.0 March 18, 2005
X80000, X80001 Typical Performance Characteristics
11.0 GATE CURRENT - SINK (mA) 10.5 10.0 tOC (s) 9.5 9.0 8.5 8.0 7.5 7.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE
(Continued)
2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 16. IGATE (SINK) vs TEMPERATURE
FIGURE 17. tFOC vs TEMPERATURE
0.800 tDELAY (NORMALIZED) 0.750 0.700 tUV (s) 0.650 tUV1 0.600 0.550 0.500 -55 -40 -25 -10 tUV2
1.02 1.00 0.98 0.96 0.94 0.92 0.90 -55
5
20
35
50
65
80
95 110 125
-35
-15
5
25
45
65
85
TEMPERATURE
TEMPERATURE
FIGURE 18. tFUV vs TEMPERATURE
FIGURE 19. tDELAYi vs TEMPERATURE
1.4 1.4 1.3 tOV (s) 1.3 1.2 1.2 1.1 1.1 1.0 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 20. tFOV vs TEMPERATURE
13
FN8148.0 March 18, 2005
X80000, X80001
VUV/OV PWRGD VOV Ref Power Good Logic VEE VUV1 Ref 2:1 MUX
VUV2 Ref BATT-ON VEE DRAIN 1V Ref 10-160A GATE Slew Rate Selection Gate Control VDD POR 5V VDD VRGO Over current logic, Hard short relay, Retry logic status and delay
FAR
VEE
IGQ1 IGQ0
VRGO
RESET VEE VEE R R x2 x1 R Programmable VOC REF R x3 x4 Control and Fault Registers Bus Interface 36R Reset Logic and Delay VEE Over current SDA SCL WP A2 A1
SENSE
MRC MRH EEPROM 2kbits 4 VEE
VEE
VRGO
OSC
Divider Reset 4
V1GOOD Select 0.1s 0.5s 1s 5s delay1 delay2 V3GOOD
EN1
V2GOOD
EN2
EN3 delay3 delay4 EN4 Delay circuit repeated 4 times VEE V4GOOD
FIGURE 21. BLOCK DIAGRAM
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FN8148.0 March 18, 2005
X80000, X80001 Pin Configuration
X80000/X80001
32-lead QFN Quad Package
PWRGD BATT-ON MRH IGQ0 IGQ1 FAR
VRGO A0 V4GOOD EN4 V3GOOD EN3 V2GOOD EN2
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
NC VEE
24 23 22 21 20 19 18 17
NC MRC WP RESET V1GOOD EN1 SCL SDA
(7mm x 7mm)
9 10 11 12 13 14 15 16
GATE
DRAIN
VDD
VEE
Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 NAME VRGO A0 V4GOOD EN4 V3GOOD EN3 V2GOOD EN2 VDD VEE VUV/OV SENSE GATE DRAIN NA A1 SDA DESCRIPTION Regulated 5V output. Used to pull-up user programmable inputs IGQ0, IGQ1, BATT-ON, A1, A0, and WP (if needed). Address Select Input. It has an internal pulldown resistor. (>10M typical) The A0 and A1 bits allow for up to 4 X80000 devices to be used on the same SMBus serial interface. V4 Voltage Good Output. This open drain output goes LOW when EN4 is less than VTRIP4 and goes HIGH when EN4 is greater than VTRIP4. There is a user selectable delay circuitry on this pin. V4 Voltage Enable Input. Fourth voltage enable pin. If unused connect to VRGO. V3 Voltage Good Output (Active Low). This open drain output goes LOW when EN3 is less than VTRIP3 and goes HIGH when EN3 is greater than VTRIP3. There is a user selectable delay circuitry on this pin. V3 Voltage Enable Input. Third voltage enable pin. If unused connect to VRGO. V2 Voltage Good Output (Active Low). This open drain output goes LOW when EN2 is less than VTRIP2 and goes HIGH when EN2 is greater than VTRIP2. There is a user selectable delay circuitry on this pin. V2 Voltage Enable Input. Second voltage enable pin. If unused connect to VRGO. Positive Supply Voltage Input. Negative Supply Voltage Input. Analog Undervoltage and Overvoltage Input. Turns off the external N-channel MOSFET when there is an undervoltage or overvoltage condition. Circuit Breaker Sense Input. This input pin detects the overcurrent condition. Gate Drive Output. Gate drive output for the external N-channel MOSFET. Drain. Drain sense input of the external N-channel MOSFET. Not Available. Do not connect to this pin. Address Select Input. It has an internal pulldown resistor. (>10M typical) The A0 and A1 bits allow for up to 4 X80000 devices to be used on the same SMBus serial interface. Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Serial Clock. The Serial Clock controls the serial bus timing for data input and output. V1 Voltage Enable Input. First voltage enable pin. If unused connect to VRGO.
18 19
SCL EN1
VUV/OV
SENSE
15
NA
A1
FN8148.0 March 18, 2005
X80000, X80001 Pin Descriptions
PIN 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME V1GOOD RESET WP MRC NC VEE NC FAR BATT-ON PWRGD IGQ1 IGQ0 MRH (Continued) DESCRIPTION V1 Voltage Good Output (Active Low).This open drain output goes LOW when EN1 is less than VTRIP1 and goes HIGH when EN1 is greater than VTRIP1. There is a user selectable delay circuitry on this pin. RESET Output. This open drain pin is an active LOW output. This pin will be active until PWRGD goes active and the power sequencing is complete. This pin will be released after a programmable delay. Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the device. It has an internal pulldown resistor. (>10M typical) Manual Reset Input Cold-side. Pulling the MRC pin HIGH initiates a system side RESET. The MRC signal must be held HIGH for 5secs. It has an internal pulldown resistor. (>10M typical) No Connect. No internal connections. Negative Supply Voltage Input. No Connect. No internal connections. Failure After Re-try (FAR) output signal. Failure After Re-try (FAR) is asserted after a number of retries. Used for Overcurrent and hardshort detection. Battery On Input. This input signals that the battery backup (or secondary supply) is supplying power to the backplane. It has an internal pulldown resistor. (>10M typical) Power Good Output. This output pin enables a power module. Gate Current Quick Select Bit 1 Input. This pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10M typical) Gate Current Quick Select Bit 0 Input. This pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10M typical) Manual Reset Input Hot-side. Pulling the MRH pin LOW initiates a GATE pin reset (GATE pin pulled LOW). The MRH signal must be held LOW for 5secs (minimum).
Functional Description
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board's power module or DC/DC converter can draw huge transient currents as they charge up (See Figure 22). This transient current can cause permanent damage to the board's components and cause transients on the system power supply.
-48V Return R4 182K 1%
The X80000 is designed to turn on a board's supply voltage in a controlled manner (see Figure 23), allowing the board to be safely inserted or removed from a live backplane. The device also provides undervoltage, overvoltage and overcurrent protection while keeping the power module (DCDC converter) off until the backplane input voltage is stable and within tolerance. IINRUSH
VGATE
UV=37V VUV/OV OV=71V VDD DC/DC Converter
R5 30k 1%
X80000 X80001
DC/DC Converter
VFET_DRAIN
DRAIN
R6 10K 1%
VEE SENSE 0.1F
GATE
Rs 0.02 5%
4.7K 100 3.3n
PWRGD
100K
-48V
Iinrush
Q1 IRFR120
-48V
FIGURE 22. TYPICAL -48V HOTSWAP APPLICATION CIRCUIT
FIGURE 23. TYPICAL INRUSH WITH GATE SLEW RATE CONTROL
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Overvoltage and Undervoltage Shutdown
The X80000 provides overvoltage and undervoltage protection circuits. When an overvoltage (VOV) or undervoltage (VUV1 and VUV2) condition is detected, the GATE pin will be immediately pulled low. The undervoltage threshold VUV1 applies to the normal operation with a main supply. The undervoltage threshold VUV2 assumes the system is powered by a battery. When using a battery backup, the BATT-ON pin is pulled to VRGO. The default thresholds have been set so the external resistance values determine the overvoltage threshold, a main undervoltage threshold and a battery undervoltage threshold. As shown in Figure 26, this circuit block contains comparators and programmable voltage references to monitor the single overvoltage and dual undervoltage trip points. During manufacturing, Intersil programmed the overvoltage and undervoltage trip points as shown in Table 1 below. Custom values are possible. A resistor divider connected between the plus and minus input voltages and the VUV/OV pin (see Figure 24) determines the overvoltage and undervoltage shutdown voltages and the operating voltage range. Using the thresholds in Table 1 and the equations of Figure 24 the desired operating voltage can be determined. Figure 25 shows the resistance values for various operating voltages.
TABLE 1. OVERVOLTAGE/UNDERVOLTAGE DEFAULT THRESHOLDS THRESHOLD MAX/MIN VOLTAGE (Note 1) 74.3 67.4 43.0 33.8 LOCKOUT VOLTAGE (Note 2) 74.9 68 42.4 33.2
VP R1 VS VUV/OV
Voltage divider:
R2 V UV OV = V S --------------------- R1 + R2
or:
R1 + R2 V S = V UV OV --------------------- R2
R2 VN
FIGURE 24. OVERVOLTAGE UNDERVOLTAGE DIVIDER
OPERATING VOLTAGE (V)
100 90 80 70 60 50 40 30 20 10 150 0
VOV VUV1 BATT-ON = VEE
Operating Voltage
BATT-ON = VRGO VUV2
158
166
175
182
190
198
206
214
R1 in k (for R2=10K)
FIGURE 25. OPERATING VOLTAGE vs RESISTOR RATIO
Battery Back Up Operations An external signal, BATT-ON, is provided to switch the undervoltage trip point. The BATT-ON signal is a LOGIC HIGH if VIHB > VEE + 4V and is a LOGIC LOW if VILB < VEE + 2V. The time from a BATT-ON input change to a valid new undervoltage threshold is 100ns. See Electrical Specifications for more details. Note: The VUV/OV pin must be limited to less than VEE + 5.5V in worst case conditions. Values for R1 and R2 must be chosen such that this condition is met. Intersil recommends R1 = 182k and R2 = 10k to conform to factory settings.
TABLE 2. SELECTING BETWEEN UNDERVOLTAGE TRIP POINTS PIN BATT-ON DESCRIPTION TRIP POINT SELECTION
SYMBOL VOV VOV VUV1 VUV2 NOTES:
DESCRIPTION Overvoltage (X80000) Overvoltage (X80001) Undervoltage 1 Undervoltage 2
FALLING 3.87V 3.51V 2.21V 1.73V
RISING 3.9V 3.54V 2.24V 1.76V
1. Max/Min Voltage is the maximum and minimum operating voltage assuming the recommended VUV/OV resistor divider. 2. Lockout voltage is the voltage where the X80000/1 turns off the FET.
Undervoltage Trip If BATT-ON = 0, Point Selection Pin VUV1 trip point is selected; If BATT-ON = 1, VUV2 trip point is selected.
VUV1 and VUV2 are undervoltage thresholds.
Overvoltage/Undervoltage Fault Condition Flags On any overvoltage or undervoltage violation, the X80000 cuts-off the GATE. This condition also sets the faultovervoltage (FOV) or fault-undervoltage1/2 (FUV1/2) bits low. These bits are readable through the SMBus. To clear the fault bits, the fault condition must first be rectified (by the 17
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X80000, X80001
system) then cleared by a write to Fault Detection Register. Please refer to FDR section. See Table 2.
TABLE 3. OVERVOLTAGE/UNDERVOLTAGE FLAG BITS SYMBOL FOV VIOLATION (ON) FOV = 0, when VUV/OV > VOV (Overvoltage) FUV1/2 = 0, when VUV/OV < VUV1/2 (Undervoltage) NORMAL (OFF) FOV = 1, when VUV/OV < VOV + 0.2V and reset by a write operation FUV1/2 = 1, when VUV/OV > VUV1/2 - 0.2V and reset by a write operation
For example a 20m sense resistor sets the overcurrent level to 2.5A. Intersil's X80000 provides a safety mechanism during insertion of the board into the back plane. During insertion of the board into the backplane large currents may be induced. In order to prevent premature shut down of the external FET, the X80000 allows for a choice of up to 4 times the overcurrent setting during insertion. After the PWRGD signal is asserted, the X80000 switches back to the normal overcurrent setting. The overcurrent threshold voltage during insertion can be changed from 50mV to 100mV, 150mV, or 200mV, by setting bits in Control Register CR4. After the Power FET turns off due to an overcurrent condition, a retry circuit turns the FET back on after a delay of tSC_RETRY. If the overcurrent condition remains, the FET again turns off. This sequence repeats until the overcurrent condition is released. There are various other options that program the retry circuit to change the number of retries or to not retry. An optional output signal, FAR, indicates a failure after retry. Overcurrent Shut-down As shown in Figure 27, this circuit block contains a resistor ladder, a comparator, a noise filter and a programmable voltage reference to monitor for overcurrent conditions. The overcurrent voltage threshold (VOC) is 50mV. This can be factory set, by special order, to any setting between 30mV and 100mV. VOC is the voltage between the SENSE and VEE pins and across the RSENSE resistor. If the selected sense resistor is 20m, then 50mV corresponds to an overcurrent of 2.5A. If an overcurrent condition is detected, the GATE is turned off, all power good indicators go inactive and an overcurrent failure bit (FOC) is set. Overcurrent Noise Filter The X80000 has a noise (low pass) filter built into the overcurrent comparator. The comparator will thus ignore current spikes shorter than 5s. Other filter options are provided by setting control bits in register CR4. The control bits set the comparator to ignore current spikes shorter that 5s, 10s or 20s and allow the filter to be turned off.
TABLE 4. NOISE FILTER FOR OVER CURRENTS F1 0 0 1 1 F0 0 1 0 1 tNF (maximum noise input pulse width) 0s 5s 10s 20s
FUV1/2
R1=182K
R2=10K -48V VUV/OV
+ VOV + VUV1 + VUV2
Overvoltage Flag
To Gate Control
Programmable VREF UV Flag
UV flag_1 Programmable VREF 2:1 Mux
To Gate Control
UV flag_2
Control & Status Registers SMBus BATT_ON
Fault Bits FOV FUV1/2 SDA SCL
Programmable VREF
FIGURE 26. PROGRAMMABLE UNDERVOLTAGE AND OVERVOLTAGE FOR PRIMARY AND BATTERY BACKUP
Overcurrent Protection (Circuit Breaker Function)
The X80000 overcurrent circuit provides the following functions: * Overcurrent shut-down of the power FET and external power good indicators. * Noise filtering of the current monitor input. * Relaxed overcurrent limits for initial board insertion. * Overcurrent recovery retry operation. * Flag of overcurrent fault condition. * Flag of overcurrent retry failure. A sense resistor, placed in the supply path between VEE and SENSE (see Figure 22) generates a voltage internal to the X80000. When this voltage exceeds 50mV, an over current condition exists and an internal "circuit breaker" trips, turning off the gate drive to the external FET. The actual overcurrent level is dependent on the value of the current sense resistor.
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Programmable Voltage Reference Overcurrent Logic and Gate Control Block 0s 2 bit 5s noise filtering 10s 20s Short-Circuit Retry Logic and System Monitors Retry Delay Fault Bit FAR_STAT Retry Counter Nretry Control Registers
Failure After Re-Try
FAR
36R
VEE
R 3x R R R 2x 1x 4x
-
+
SMBus
SCL SDA
-48V
RSense Overcurrent Event
FIGURE 27. OVERCURRENT DETECTION/SHORT CIRCUIT PROTECTION WITH PROGRAMMBLE RETRY AND FLAG MONITORS
Overcurrent During Insertion Insertion is defined as the first plug-in of the board to the backplane. In this case, the X80000 is initially fully powered off prior to the hot plug connection to the mains supply. This condition is different from a situation where the mains supply has temporarily failed resulting in a partial recycle of the power. This second condition will be referred to as a power cycle. During insertion, the board can experience high levels of current for short periods of time as power supply capacitors charge up on the power bus. To prevent the overcurrent sensor from turning off the FET inadvertently, the X80000 has the ability to allow more current to flow through the powerFET and the sense resistor for a short period of time until the FET turns on and the PWRGD signal goes active. In the standard setting, 200mV is allowed across sense resistor the during insertion (10A assuming a 20mW resistor). Two bits in register CR4 select the insertion current limit of 1X, 2X, 3X or 4X the base setting of 50mV. This provides a mechanism to reduce insertion issues associated with huge current surges.
TABLE 5. INSERTION OVERCURRENT THRESHOLD OPTIONS VS1 0 0 1 1 VS0 0 1 0 1 VOCI 50mV (1X) 100mV (2X) 150mV (3X) 200mV (4X)
still exists, the FET turns off and a retry counter (SC_Counter) increments. After the selected number of failed trys, the X80000 sets a Failed After Retry Status (FAR_STAT) fault bit, sets the FAR pin LOW and goes into an idle state. In this state the GATE pin will not go active until the device is cleared. The retry circuit can be programmed to handle the retry operation in one of eight ways (See Table 6). The options allow retries from zero to unlimited and specifies when to assert the FAR (Failure After Re-Try) signal. In the "Always Retry" case there is no idle state, so when the overcurrent condition clears, the GATE goes active and the FET turns on. There are four optional retry delay periods. These are 100ms, 500ms, 1s, and 5s. These are programmed by bits located in the CR2 register. After FAR is asserted, there are two ways to clear the hardshort protection: 1. Master Reset Hot Side. The master reset pin, MRH, can be asserted by pulling it LOW. Upon MRH assertion, all default values are restored and the retry is cleared. 2. Power cycle the part, turning VDD OFF, then ON. If an overcurrent condition does not occur on any retry, the gate pin will proceed to open at the user defined slew rate. Overcurrent Fault Condition Flags On any overcurrent violation, the X80000 will cut-off the GATE, turning off the voltage to the load, and setting all power good pins to their disabled state. In this condition, the fault-overcurrent bit (FOC) goes LOW. To clear FOC, remove the over current condition, then write to the control register. Refer to instructions on writing to the FDR (See Table 8).
Hardshort Protection - Programmable Retry In the event on an overcurrent or hard short condition, the X80000 includes a retry circuit. This circuit waits for 100ms, then attempts to again turn on the FET. If the fault condition
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X80000, X80001
When exceeding the overcurrent retry limit, the status bit "FAR_STAT" is set to `1' and the FAR pin is asserted. To clear FAR_STAT, write to the control register. Refer to instructions on writing to the FDR (See Table 9).
TABLE 6. RETRY AND EVENT SEQUENCE OPTIONS NR2 NR1 NR0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 NRETRY AND RETRY SEQUENCE OF EVENTS (FAILURE MODE) Always Retry, Do Not assert FAR pin (Default) NRETRY = 1 (one retry), assert FAR pin after NRETRY, STOP retry, and shutoff GATE pin NRETRY = 2 (two retries), assert FAR pin after NRETRY, STOP retry, and shutoff GATE pin NRETRY = 3 (three retries), assert FAR pin after NRETRY, STOP retry, and shutoff GATE pin NRETRY = 4 (four retries), assert FAR pin after NRETRY, STOP retry, and shutoff GATE pin NRETRY = 5 (five retries), assert FAR pin after NRETRY, STOP retry, and shutoff GATE pin Always Retry, assert FAR pin after 1st retry; clear FAR when FOC cleared, do not shutoff GATE pin. NRETRY = 0 (no retry), asset FAR, and shutoff GATE pin.
The X80000 provides an IGATE current of 50A to provide on-chip slew rate control to minimize inrush current. This current is programmable from 10A to 160uA (in 10A steps) to allow the X80000 to support various load conditions (See Figure 23 and Figure 28). IGATE is chosen to limit the inrush current and to provide the best charge time for a given load, while avoiding overcurrent conditions. The user programs the IGATE current using four IGATE control bits.
IGATE =160A 100A INRUSH CURRENT 75A 25A 10A Overcurrent IGATE
T1
T2 T3 T4 TIME (ms)
T5
FIGURE 28. SELECTING IGATE CURRENT FOR SLEW RATE CONTROL ON THE GATE PIN
1
1
1
TABLE 7. RETRY EVENT DELAY OPTIONS TSC1 0 0 1 1 TSC0 0 1 0 1 tSC_RETRY, DELAY BETWEEN RETRIES 100 miliseconds 500 miliseconds 1 second 5 seconds
For applications that require different ramp rates during insertion and start-up and operations modes, the X80000 provides two external pins, IGQ1 and IGQ0, that allow the user to switch to different GATE currents on-the-fly by selecting one of four pre-selected IGATE currents. When IGQ0 and IGQ1 are left unconnected, the gate current is determined by the gate control bits. The other three settings are 10A, 70A and 150A. Typically, the delay from IGQ1 and IGQ0 selection to a change in the GATE pin current is less than 1 second.
Programmable Slew Rate (Gate) Control
As shown in Figure 29, this circuit block contains a selectable current source (IGATE) that drives the 50A current into the GATE pin. This current provides a controlled slew rate for the FET. X80000 allows the user to change the gate current to one of sixteen possible IGATE values. The options allow currents of between 10A to 160A in 10A increments. Once the overcurrent condition and the amount of load is known, an appropriate slew rate can be determined and selected for the external FET. This will ensure proper
TABLE 8. OVERCURRENT FLAG BIT STATUS BIT VIOLATION (ON) FOC FOC = 0, when VRSENSE > VOC NORMAL (OFF) FOC = 1, when: VRSENSE < VOC - 0.2V and reset by a write operation or hardshort retry is initiated.
TABLE 9. RETRY COUNT FAILURE STATUS BIT STATUS BIT FAR_STAT CONDITION if FAR_STAT = 1, FAR is asserted. if FAR_STAT = 0, FAR is deasserted
Gate Drive Output Slew Rate (Inrush Current) Control
The gate output drives an external N-Channel FET. The GATE pin goes high when no overcurrent, undervoltage or overvoltage conditions exist.
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operation to control Inrush currents during hot insertion modes.
Gate Current Quick Select Logic
VDD=12V 10A to 160A Slew Rate Selection Logic
IGQ1 IGQ0
Control Registers SCL SDA
voltage from rising and keep the FET from turning on. However, unless VDD powers up very quickly, there will be a brief period of time during initial application of power when the X80000 circuits cannot hold the gate low. The use of an external capacitor (C1) prevents this. Capacitors C1 and C2 form a voltage divider to prevent the gate voltage from rising above the FET turn on threshold before the X80000 can hold the gate low. Use the following formula for choosing C1.
V1 - V2 C1 = --------------------C2 V2
VEE
SENSE GATE
DRAIN
SMBus
Where:
100nF* R2 100* 22K C2 3.3nF
V1 = Maximum input voltage,
100K
V2 = FET threshold Voltage, C1 = Gate capacitor,
-48V RSENSE IINRUSH
LOAD
C2 = Feedback capacitor. In a system where VDD rises very fast, a smaller value of C1 may suffice as the X80000 will control voltage at the gate before the voltage can rise to the FET turn on threshold. The circuit of Figure 29 assumes that the input voltage can rise to 80V before the X80000 sees operational voltage on VDD. If C1 is used then the series resistor R1 will be required to prevent high frequency oscillations.
* Optional Components See Section "Gate Capacitor, Filtering and Feedback"
FIGURE 29. PROGRAMMBLE SLEW RATE (INRUSH CURRENT) CONTROL
Software Slew Rate Control Users can adjust the slew rate control by using an SMBus write command to change the slew rate control bits. This allows adaptation in the case of changing load conditions, creates a modular design for downstream DC-DC supplies, and provides control of the load on the hot voltage when slew rates vs. loads vary. Gate Capacitor, Filtering and Feedback In Figure 29, the FET control circuit includes an FET feedback capacitor C2, which provides compensation for the FET during turn on. The capacitor value depends on the load, the FET gate current, and the maximum desired inrush current. The value of C2 can be selected with the following formula:
I GATE x C LOAD C2 = -----------------------------------------I INRUSH
TABLE 10. IGATE OUTPUT CURRENT OPTIONS IG3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IG1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IG0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 IGATE (A) 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Default
Where: IGATE = FET Gate current IINRUSH = Maximum desired inrush current CLOAD = DC/DC bulk capacitance With the X80000, there is some control of the gate current with the IGQ pins and IGx bits, so one selection of C2 can cover a wide range of possible loading conditions. Typical values for C2 range from 2.2 to 4.7nF. When power is applied to the system, the FET tries to turn on due to its internal gate to drain capacitance (Cgd) and the feedback capacitor C2 (see Figure 29). The X80000 device, when powered, pulls the gate output low to prevent the gate
GATE Current Quick Selection For applications that require different ramp rates during insertion and start-up and operations modes or those where the serial interface is not available, the X80000 provides two
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external pins, IGQ1 and IGQ0, that allow the system to switch to different GATE current on-the-fly with pre-selected IGATE currents. The IGQ1 and IGQ0 pins can be used to select from one of four set values.
IGQ1 PIN 0 0 1 1 IGQ0 PIN 0 1 0 1 CONTENTS Defaults to gate current set by IG3:IG0 bits Gate Current is 10A Gate Current is 70A Gate Current is 150A
VEE SENSE GATE DRAIN 100K - + VDRAIN Power Good Logic
PWRGD
- +
VEE
1V (Factory Programmable)
Control/Status Registers SCL SDA
VGATE SMBus VDD-1V
Typically, the delay from IGQ1 and IGQ0 selection to a change in the GATE pin current is less than 1 second.
Drain Sense and Power Good Indicator
The X80000 provides a drain sense and power good indicator circuit. The PWRGD signal asserts LOW when there is no overvoltage, no undervoltage, and no overcurrent condition, the Gate voltage exceeds VDD-1V, and the voltage at the DRAIN pin is less VEE+VDRAIN. As shown in Figure 30, this circuit block contains a drain sense voltage trip point (VDRAIN) and a gate voltage trip point (VGATE), two comparators, and internal voltage references. These provide both a drain sense and a gate sense circuit to determine the whether the FET has turned on as requested. If so, the power good indicator (PWRGD) goes active. The drain sense circuit checks the DRAIN pin. If the voltage on this pin is greater that 1V above VEE, then a fault condition exists. The gate sense circuit checks the GATE pin. If the voltage on this pin is less than VEE - 1V, then a fault condition exists. The PWRGD signal asserts (Logic LOW) only when all of the below conditions are true: * there is no overvoltage or no undervoltage condition, (i.e. undervoltage < VEE < overvoltage.) * There is no overcurrent condition (i.e. VEE - VSENSE < VOC.) * The FET is turned on (i.e. VDRAIN < VEE + 1V and VGATE > VDD - 1V).
-48V RSENSE
LOAD
FIGURE 30. DRAIN SENSE AND POWER GOOD INDICATOR
Power On Reset and System Reset With Delay
Application of power to the X80000 activates a Power On Reset circuit that pulls the RESET pin active. This signal, if used, provides several benefits. * It prevents the system microprocessor from starting to operate with insufficient voltage. * It prevents the processor from operating prior to stabilization of the oscillator. * It allows time for an FPGA to download its configuration prior to initialization of the circuit. * It prevents communication to the EEPROM during unstable power conditions, greatly reducing the likelihood of data corruption on power up. The SPOR/RESET circuit is activated when all voltages are within specified ranges and the following time-out conditions are met: PWRGD and V1GOOD, V2GOOD, V3GOOD, and V4GOOD. The SPOR/RESET circuit will then wait 100ms and assert the RESET pin. The SPOR delay may be changed by setting the TPOR bits in register CR2. The delay can be set to 100 ms, 500 ms, 1 second, or 5 seconds.
TABLE 11. SPOR RESET DELAY OPTIONS TPOR1 0 0 1 1 TPOR0 0 1 0 1 tSPOR DELAY BEFORE RESET ASSERTION 100 miliseconds (default) 500 miliseconds 1 second 5 seconds
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Fault Detection Register
VRGO
OSC
Divider Reset 4
SMBus Interface Control Register
4 V1GOOD Select 0.1s 0.5s 1s 5s delay1 delay2 V3GOOD
EN1
V2GOOD
EN2
EN3 delay3 delay4 EN4 Delay circuit repeated 4 times VEE V4GOOD
FIGURE 32. VOLTAGE ENABLE CONTROL AND VGOOD OUTPUTS
delay time can be changed by setting bits in register CR2 (See Figure 32).
Drain Sense & Power Good Logic Enable Logic ViGOOD i = 1 to 4 SPOR RESET P RESET Logic tSPOR Delay VEE MRC Bus Interface Control Remote & Fault Registers PWRGD
As shown in Figure 32, this circuit block contains four separate voltage enable inputs, a time delay circuit, and an output driver.
TABLE 12. ViGOOD OUTPUT TIME DELAY OPTIONS
VDD
TiD1 0 0 1 1
TiD0 0 1 0 1
tDELAYi 100ms 500ms 1 secs 5 secs
where i is the ith voltage enable (i = 1 to 4).
SDA
Manual Reset and Remote Shutdown
The manual reset option allows a hardware reset of either the Gate control or the PWRGD indicator. These can be used to recover the system in the event of an abnormal operating condition. The remote shutdown feature of the X80000 allows smart power control remotely through the SMBus. The host system can either override the control of the FET, thus turning it off, or it can remove the override. Removing the override restarts the power up sequence. The X80000 has two manual reset pins: MRH (manual reset hot side) and MRC (manual reset cold side). The MRH signal is used as a manual reset for the GATE pin. This pin is used to initiate Soft Reinsert. When MRH is pulled LOW the GATE pin will be pulled LOW. It also clears the Remote Shutdown Register (RSR) and the FAR signal. When the MRH pin goes HIGH, it removes the override signal and the
SCL
EEPROM 2Kbits
FIGURE 31. POWER ON/SYSTEM RESET AND DELAY (BLOCK DIAGRAM)
Quad Voltage Monitoring
X80000 monitors 4 voltage enable inputs. When the ENi (i=1-4) input is detected to be below the input threshold, the output ViGOOD (i = 1 to 4) goes active. The ViGOOD signal is asserted after a delay of 100ms. This delay can be changed on each ViGOOD output individually with bits in register CR3. The delay can be 100ms, 500ms, 1s and 5s. The ViGOOD signal remains active low until ENi rises above threshold. Once the PWRGD signal is asserted, the power sequencing of the DC-DC modules can commence. RESET will go active 100ms after all ViGOOD (i=1 to 4) outputs are asserted. This
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gate will turn on based on the selected gate control mechanism.
TABLE 13. MANUAL RESET OF THE HOT SIDE (GATE SIGNAL) MRH 1 GATE PIN Operational REQUIREMENTS When MRH is HIGH the Manual Reset (Hot) function is disabled and the device operates normally MRH must be held LOW minimum of 5secs to turn of the GATE
Flexible Power Sequencing of Multiple Power Supplies
The X80000 provides several circuits such as multiple voltage enable pins, programmable delays, and a power good signals that can be used to set up flexible power sequencing schemes for downstream DC-DC supplies. Below are two examples: 1. Power Up of DC-DC Supplies In Parallel Sequencing Using Programmable Delays on Power Good (See Figure 33 and Figure 34). Several DC-DC power supplies and their respective power up start times can be controlled using the X80000 such that each of the DC-DC power supplies will start up following the issue of the PWRGD signal. The PWRGD signal is fed into the ENi inputs to the X80000. When PWRGD is valid, the internal voltage enable inputs issue ViGOOD signals after a time delay. The ViGOOD signals control the ON/OFF pins of the DC-DC supplies. In the factory default condition, each DC/DC converter is instructed to turn on 100ms after the PWRGD goes active. However, each ViGOOD delay is individually selectable as 100ms, 500ms, 1s and 5s. The delay times are changed via the SMBus during calibration of the system. 2. Power Up of DC-DC Supplies Via Relay Sequencing Using Power Good and Voltage Enables (see Figure 35 and Figure 36). Several DC-DC power supplies and their respective power up start times can be controlled using the X80000 such that each of the DC-DC power supplies will start in a relay sequencing fashion. The 1st DC-DC supply will power up when PWRGD is LOW after a 100ms delay. Subsequent DC-DC supplies will power up after the prior supply has reached its operating voltage. One way to do this is by using an external CPU Supervisor (for example the Intersil X40430) to monitor the DC-DC output. When the DC/DC voltage is good, the supervisor output signals the X80000 EN1 input to sequence the next supply. An opto-coupler is recommended in this connection for isolation. This configuration ensures that each subsequent DC-DC supply will power up after the preceding DC-DC supplys voltage output is valid. Again, the X80000 offers programmable delays for each voltage enable input that is selectable via the SMBus during calibration of the system.
0
OFF
The MRC signal is used as a manual reset for the PWRGD signal. This pin is used to initiate a Soft Restart. When the MRC is pulled HIGH, the PWRGD signal is pulled HIGH. When MRC pin goes LOW, the PWRGD pin goes low using the MRC pin has no affect on the FET gate control, so the FET remains on.
TABLE 14. MANUAL RESET OF THE COLD SIDE (PWRGD SIGNAL) MRC 1 0 PWRGD HIGH Operational Requirements MRC must be held HIGH minimum of 5secs to set PWRGD HIGH When MRC is LOW the MRC function is disabled and the device operates normally
Fault Detection
The X80000 contains a Fault Detection Register (FDR) that provides the user the status of the causes for a RESET pin active (See Table 17). At power-up, the FDR is defaulted to all "0". The system needs to initialize the register to all "1" before the actual monitoring can take place. In the event that any one of the monitored sources fail, the corresponding bit in the register changes from a "1" to a "0" to indicate the failure (ViGOOD sources set the bit LOW when the ViGOOD goes LOW indicating a "good" status). When a RESET is detected by the main controller, the controller should read of the FDR and note the cause of the fault. After reading the register, the controller can reset the register bit back to all "1" in preparation for future monitored conditions.
Remote Shutdown
The gate of the external MOSFET can be remotely shutdown by using a software command sequence. A byte write of `10101010' (AAh) data to the Remote Shutdown Register (RSR) will shutdown the gate and the gate will be pulled low. Activating the MRH pin or a writing 00h into the RSR will turn off the override signal and the gate will turn on based on the gate control mechanism. The RSR powers up with `0's in the register and its contents are volatile.
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FN8148.0 March 18, 2005
X80000, X80001
-48V Return
MRH R4 182K 1%
MRC
V4GOOD EN4 V3GOOD EN3
UV=37V VUV/OV OV=71V VDD X80000 X80001
R5 30K 1%
V2GOOD EN2 V1GOOD EN1
R6 10K 1%
VEE
SENSE 0.1F
GATE
DRAIN RESET PWRGD
Rs -48V 0.02 5% Q1 IRFR120
4.7K 100 3.3n 100K
OPTO COUPLER
OPTO COUPLER
PWRGD
RESET
-48V Return
1 C3 + 0.1F 100V C4 100F 100V 4
ON/OFF VIN+ VOUT+ SENSE+ TRIM SENSEVINVOUT
9 8 7 6 5
3.3V + C5 100F 16V
RESET VCC1 VCC2 C
-48V Return
1 C6 + 0.1F 100V C7 100F 100V 4
ON/OFF VIN+ VOUT+ SENSE+ TRIM SENSEVINVOUT
9 8 7 6 5
2.5V + C8 100F 16V
VCC1 VCC2 FPGA
-48V Return
1 C9 + 0.1F 100V C10 100F 100V 4
ON/OFF VIN+ VOUT+ SENSE+ TRIM SENSEVINVOUT
9 8 7 6 5
1.8V + C11 100F 16V
VCC1 VCC2 ASIC
-48V Return
1 C12 + 0.1F 100V C13 100F 100V 4
ON/OFF VIN+ VOUT+ SENSE+ TRIM SENSEVOUT VIN-
9 8 7 6 5
1.2V + C14 100F 16V
FIGURE 33. TYPICAL APPLICATION OF HOTSWAP AND DC-DC PARALLEL POWER SEQUENCING
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FN8148.0 March 18, 2005
X80000, X80001
FET turns ON EN2 In (from PWRGD) tDELAY1 Programmable Delay
100ms 500ms 1sec 5sec
Select tDELAYx and tRESET via the 2-wire interface.
V1GDO Power Supply #1 OUTPUT (3.3V) EN2 tDELAY2 V2GDO Power Supply #2 OUTPUT (2.5V) EN3
Power Supply #1 turns ON 100ms 500ms 1sec 5sec Programmable Delay Power Supply #2 turns ON 100ms 500ms 1sec 5sec
tDELAY3
Programmable Delay Power Supply #3 turns ON 100ms 500ms 1sec 5sec
V3GDO Power Supply #3 OUTPUT (1.8V) EN4 tDELAY4 Programmable Delay
V4GDO Power Supply #4 OUTPUT (1.2V) tRESET RESET
Power Supply #4 turns ON
100ms 500ms 1sec 5sec
Programmable Delay
FIGURE 34. PARALLEL SEQUENCING OF DC-DC SUPPLIES (TIMING)
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FN8148.0 March 18, 2005
X80000, X80001
UV=37V VUV/OV OV=71V VDD X80000 X80001
R5 30k 1%
V2GOOD EN2 V1GOOD EN1
VFAIL<1:3>
-48V Return
MRH R4 182k 1%
MRC
OPTO COUPLER
V4GOOD EN4 V3GOOD EN3
X40430 (Optional)
R6 10k 1%
VEE
SENSE 0.1F
GATE
DRAIN RESET PWRGD
OPTO COUPLER
VMON<1:3>
Rs -48V 0.02 5% Q1 IRFR120
4.7K 100 3.3n 100K
OPTO COUPLER PWRGD RESET
-48V Return
1 C3 + 0.1F 100V C4 100F 100V 4
ON/OFF VOUT+ VIN+ SENSE+ TRIM SENSEVINVOUT
9 8 7 6 5
3.3V + C5 100F 16V
RESET VCC1 VCC2 C
-48V Return
1 C6 + 0.1F 100V C7 100F 100V 4
ON/OFF VOUT+ VIN+ SENSE+ TRIM SENSEVINVOUT
9 8 7 6 5
2.5V + C8 100F 16V
VCC1 VCC2 FPGA
-48V Return
1 C9 + 0.1F 100V C10 100F 100V 4
ON/OFF VOUT+ VIN+ SENSE+ TRIM SENSEVINVOUT
9 8 7 6 5
1.8V + C11 100F 16V
VCC1 VCC2 ASIC
-48V Return
1 C12 + 0.1F 100V C13 100F 100V 4
ON/OFF VOUT+ VIN+ SENSE+ TRIM SENSEVINVOUT
9 8 7 6 5
1.2V + C14 100F 16V
FIGURE 35. TYPICAL APPLICATION OF HOTSWAP AND DC-DC RELAY SEQUENCING
27
FN8148.0 March 18, 2005
X80000, X80001
FET turns ON EN2 In (from PWRGD) tDELAY1 Programmable Delay
100ms 500ms 1sec 5sec
Select tDELAYx and tRESET via the 2-wire interface.
V1GDO Power Supply #1 OUTPUT (3.3V) EN2 tDELAY2 V2GDO Power Supply #2 OUTPUT (2.5V) EN3
Power Supply #1 turns ON V2MON threshold 100ms 500ms 1sec 5sec
Programmable Delay Power Supply #2 turns ON V3MON threshold 100ms 500ms 1sec 5sec
tDELAY3
Programmable Delay Power Supply #3 turns ON V4MON threshold 100ms 500ms 1sec 5sec
V3GDO Power Supply #3 OUTPUT (1.8V) EN4 tDELAY4
Programmable Delay Power Supply #4 turns ON
V4GDO Power Supply #4 OUTPUT (1.2V) tRESET RESET
100ms 500ms 1sec 5sec
Programmable Delay
FIGURE 36. RELAY SEQUENCING OF DC-DC SUPPLIES (TIMING)
Control Registers and Memory
The user addressable internal control, status and memory components of the X80000 can be split up into four parts: * Control Register (CR) * Fault Detection Register (FDR) * Remote Shutdown Register (RSR) * EEPROM array
Registers
The Control Registers, Remote Shutdown Register and Fault Detection Register are summarized in Table 15. Changing bits in these registers change the operation of the device or clear fault conditions. Reading bits from these registers provides information about device configuration or fault conditions. Reads and writes are done through the SMBus serial port. It is important to remember that, in most cases, the SMBus serial port must be isolated between the X80000, which is referenced to -48V, and the system controller, which is referenced to ground.
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FN8148.0 March 18, 2005
X80000, X80001
All of the Control Register bits are nonvolatile (except for the WEL bit), so they do not change when power is removed. The values of the Register Block can be read at any time by performing a random read (see Serial Interface) at the specific byte address location. Only one byte is read by each register read operation. Bits in the registers can be modified by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation.
TABLE 15. REGISTER ADDRESS MAP BYTE REGISTER ADDR. NAME 00H 01H 02H 03H 04H 05H CR0 CR1 CR2 CR3 CR4 RSR (Note 1) FDR BIT DESCRIPTION Control Register 0 Control Register 1 Control Register 2 Control Register 3 Control Register 4 Remote Shutdown Register Fault Detection Register 7 WEL WPEN IG3 T4D1 VS1 6 0 0 IG2 T4D0 VS0 5 0 0 IG1 T3D1 F1 4 0 BP1 IG0 T3D0 F0 3 0 BP0 TPOR1 T2D1 0 2 0 NR2 TPOR0 T2D0 0 1 0 NR1 TSC1 T1D1 0 0 0 NR0 TSC0 T1D0 0 MEMORY TYPE Volatile EEPROM EEPROM EEPROM EEPROM Volatile
AAh: Override FET control and shutdown the FET 00h: Turn off override (All other data combinations to RSR are reserved.) FOV FUV1/2 FOC FAR_ STAT V40S V30S V20S V10S
FF
Volatile
(1) This register is write only TABLE 16. FAULT DETECTION BITS SUMMARY LOCATION(S) SYMBOL FAR_STAT FOC FOV FUV1/2 V1OS V2OS V3OS V4OS REGISTER FDR FDR FDR FDR FDR FDR FDR FDR BITS 4 5 7 6 0 1 2 3 CONTROL FUNCTION/ STATUS INDICATION Retry Violation Overcurrent Violation Overvoltage Violation Undervoltage Violation 1st Voltage Good 2nd Voltage Good 3rd Voltage Good 4th Voltage Good DESCRIPTION FAR_STAT = 0 : Failure After retry detected (must be preset to 1). FOC = 0 : Over current detected (must be preset to 1). FOV = 0 : Over voltage detected (must be preset to 1). FUV1/2 = 0 : Under voltage detected (must be preset to 1). V1OS = 0 : V1GOOD pin has been asserted (must be preset to 1). V2OS = 0 : V2GOOD pin has been asserted (must be preset to 1). V3OS = 0 : V3GOOD pin has been asserted (must be preset to 1). V4OS = 0 : V4GOOD pin has been asserted (must be preset to 1).
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FN8148.0 March 18, 2005
X80000, X80001
TABLE 17. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY LOCATION(S) SYMBOL REGISTER BITS SOFTWARE CONTROL BITS F0 F1 CR4 5:4 Insertion Current Filter F1=0, F0=0 ; tNF = 0 F1=0, F0=1 ; tNF = 5s F1=1, F0=0 ; tNF = 10s F1=1, F0=1 ; tNF = 20s See Table 10. CONTROL FUNCTION/ STATUS INDICATION DESCRIPTION
IG0 IG1 IG2 IG3 NR0 NR1 NR2 T1D0 T1D1 T2D0 T2D1 T3D0 T3D1 T4D0 T4D1 TPOR0 TPOR1
CR2
7:4
Gate Current Select
CR1
2:0
Retry Sequence Options
See Table 6.
CR3 CR3 CR3 CR3 CR2
1:0 3:2 5:4 7:6 3:2
V1GOOD Time Delay V2GOOD Time Delay V3GOOD Time Delay V4GOOD Time Delay RESET delay time
TiD1=0, TiD0=0 : ViGOOD delay = 100ms TiD1=0, TiD0=1 : ViGOOD delay = 500ms TiD1=1, TiD0=0 : ViGOOD delay = 1s TiD1=1, TiD0=1 : ViGOOD delay = 5s
TPOR1=0, TPOR0=0 : RESET delay = 100ms TPOR1=0, TPOR0=1 : RESET delay = 500ms TPOR1=1, TPOR0=0 : RESET delay = 1s TPOR1=1, TPOR0=1 : RESET delay = 5s TSC1=0, TSC0=0 ; tSC_RETRY = 100ms TSC1=0, TSC0=1 ; tSC_RETRY = 500ms TSC1=1, TSC0=0 ; tSC_RETRY = 1s TSC1=1, TSC0=1 ; tSC_RETRY = 5s VS1=0, VS0=0 ; Insertion Overcurrent Limit = 1X VS1=0, VS0=1 ; Insertion Overcurrent Limit = 2X VS1=1, VS0=0 ; Insertion Overcurrent Limit = 3X VS1=1, VS0=1 ; Insertion Overcurrent Limit = 4X WEL = 1 enables write operations to the control registers and EEPROM. WEL = 0 prevents write operations. WPEN = 1 (and WP pin HIGH) prevents writes to the control registers and the EEPROM. BP1=0, BP0=0 : No EEPROM memory protected. BP1=0, BP0=1 : Upper 1/4 of EEPROM memory protected BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected. BP1=1, BP0=1 : All of EEPROM memory protected.
TSC0 TSC1
CR2
1:0
Overcurrent Retry Delay Time
VS0 VS1
CR4
7:6
Insertion Overcurrent Limit
WEL WPEN BP1 BP0
CR0 CR1 CR1
7 7 4:3
Write Enable Write Protect EEPROM Block Protect
HARDWARE SELECT BITS IGQ0 IGQ1 Input pins Gate Current Select IGQ1=0, IGQ0=0 : IGATE = set by IG0-IG3 IGQ1=0, IGQ0=1 : IGATE = 10A IGQ1=1, IGQ0=0 : IGATE = 70A IGQ1=1, IGQ0=1 : IGATE = 150A BATTON = 0 ; Undervoltage Threshold = VUV1 BATTON = 1 ; Undervoltage Threshold = VUV2
BATTON
Input pin
Main or Battery
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FN8148.0 March 18, 2005
X80000, X80001 Memory
The X80000 contains a 2kbit EEPROM memory array. This array can contain information about manufacturing location and dates, board configuration, fault conditions, service history, etc. Access to this memory is through the SMBus serial port. Read and write operations are similar to those of the control registers, but a single command can write up to 16 bytes at one time. A single read command can return the entire contents of the EEPROM memory. Note, a write to FDR or RSR does not require that WEL=1.
BP1 and BP0: Block Protect Bits
The Block Protect Bits, BP1 and BP0, determines which blocks of the memory array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of four segments of the array.
PROTECTED ADDRESSES (SIZE) None (Default) C0h - FFh (64 bytes) 80h - FFh (128 bytes) 00h - FFh (256 bytes) BP1 BP0 ARRAY LOCK None (Default) Upper 1/4 Upper 1/2 All
Register and Memory Protection
In order to reduce the possibility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the X80000. These are a Write Enable Latch, Block Protect bits, a Write Protect Enable bit and a Write Protect pin.
0 0 1 1
0 1 0 1
WEL: Write Enable Latch
A write enable latch (WEL) bit controls write accesses to the nonvolatile registers and the EEPROM memory array in the X80000. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address (registers or memory) will be ignored. The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the control register 0 (CR0). It is important to write only 00h or 80h to the CR0 register. Once set, WEL remains set until either it is reset to 0 (by writing a "0" to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again.
WPEN: Write Protect Enable
The Write Protect pin and Write Protect Enable bit in the CR1 register control the Programmable Hardware Write Protect feature. Hardware Protection is enabled when the WP pin is HIGH and WPEN bit is HIGH and disabled when WP pin is LOW or the WPEN bit is LOW. When the chip is Hardware Write Protected, non-volatile writes to all control registers (CR1, CR2, CR3, and CR4) are disabled including BP bits, the WPEN bit itself, and the blocked sections in the memory Array. Only the section of the memory array that are not block protected can be written.
TABLE 18. WRITE PROTECT CONDITIONS MEMORY ARRAY NOT BLOCK PROTECTED Writes Blocked Writes Enabled Writes Enabled Writes Enabled MEMORY ARRAY BLOCK PROTECTED Writes Blocked Writes Blocked Writes Blocked Writes Blocked WRITES TO CR1, CR2, CR3, CR4 Writes Blocked Writes Enabled Writes Enabled Writes Blocked
WEL LOW HIGH HIGH HIGH
WP X LOW HIGH HIGH
WPEN X X LOW HIGH
PROTECTION Hardware Software Software Hardware
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FN8148.0 March 18, 2005
X80000, X80001 Bus Interface Information
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state.
SCL
SDA
Start
Stop
FIGURE 37. VALID START AND STOP CONDITIONS
Serial Clock and Data
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (See Figure 37).
SCL from Master Data Output from Transmitter
1
8
9
Serial Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Data Output from Receiver Start Acknowledge
FIGURE 38. ACKNOWLEDGE RESPONSE FROM RECEIVER
Serial Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH, followed by a HIGH to LOW transition of SCL. The stop condition is also used to place the device into the Standby power mode after a read sequence.
Device Addressing
Addressing Protocol Overview
Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being clocked into the SMBus port on the SCL and SDA pins. The Slave address selects the part of the device to be addressed, and specifies if a Read or Write operation is to be performed.
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (See Figure 38). The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop
Slave Address Byte
Following a START condition, the master must output a Slave Address Byte. This byte consists of three parts: * The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). The
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FN8148.0 March 18, 2005
X80000, X80001
Device Type Identifier MUST be set to 1010 in order to select the device. * The next two bits (SA3 - SA2) are slave address bits. The bits received via the SMBus are compared to A0 and A1 pins and must match or the communication is aborted. * The next bit, SA1, selects the device memory sector. There are two addressable sectors: the memory array and the control, fault detection and remote shutdown registers. * The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed. When the R/W bit is "1", then a READ operation is selected. A "0" selects a WRITE operation (Refer to Figure 39).
DEVICE TYPE IDENTIFIER EXTERNAL DEVICE ADDRESS SA4 SA3 SA2 Memory READ / Select WRITE
memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. A write to a protected block of memory will suppress the acknowledge bit. Page Write The device is capable of a page write operation (See Figure 40). It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to `0' on the same page (See Figure 41). This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Stop and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master's byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation (See Figure 44).
SA7
SA6
SA5
SA1 MS
SA0 R/W
1
0
1
0
A1
A0
INTERNAL ADDRESS (SA1) 0 1
INTERNALLY ADDRESSED DEVICE EEPROM Array Control Register, Fault Detection Register, Remote Shutdown Register
BIT SA0 0 1
OPERATION WRITE READ
FIGURE 39. SLAVE ADDRESS FORMAT
Serial Write Operations
In order to perform a write operation to either a Control Register or the EEPROM array, the Write Enable Latch (WEL) bit must first be set. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile 33
FN8148.0 March 18, 2005
X80000, X80001
(1 to n to 16) Signals from the Master S t a r t Slave Address Byte Address Data (1) Data (n) S t o p
SDA Bus 1010 Signals from the Slave
0 A C K A C K A C K A C K
FIGURE 40. PAGE WRITE OPERATION
7 Bytes
5 Bytes
address =6
address pointer ends here Addr = 7
address 10
address n-1
FIGURE 41. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10
Signals from the Master
S t a r t
Slave Address
Byte Address
S t a r t
Slave Address
S t o p 1 A C K
SDA Bus
1010
0 A C K A C K
1010
Signals from the Slave
Data
FIGURE 42. RANDOM ADDRESS READ SEQUENCE
Signals from the Master
S t a r t
Slave Address
S t o p
SDA Bus
1010
1 A C K
Signals from the Slave
Data
FIGURE 43. CURRENT ADDRESS READ SEQUENCE
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FN8148.0 March 18, 2005
X80000, X80001
Current Address Read
Byte Load Completed by Issuing STOP. Enter ACK Polling
Issue START
Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. See Figure 43 or the address, acknowledge, and data transfer sequence.
Issue Slave Address Byte (Read or Write)
Issue STOP
NO ACK Returned?
YES
Operational Notes
The device powers-up in the following state: * The device is in the low power standby state. * The WEL bit is set to `0'. In this state, it is not possible to write to the device. * SDA pin is the input mode.
High Voltage Cycle Complete. Continue Command Sequence? NO
Issue STOP
YES Continue Normal Read or Write Command Sequence
Data Protection
The following circuitry has been included to prevent inadvertent writes: * The WEL bit must be set to allow write operations. * The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle.
PROCEED
FIGURE 44. ACKNOWLEDGE POLLING SEQUENCE
Serial Read Operations
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 42 for the address, acknowledge, and data transfer sequence.
35
FN8148.0 March 18, 2005
X80000, X80001 Packaging Information
32-Lead Very Very Thin Quad Flat No Lead Package 7mm x 7mm Body with 0.65mm Lead Pitch
0.000 (0.00) 0.002 (0.05)
0.007 (0.19) 0.009 (0.25)
0.009 (0.23) 0.015 (0.38)
0.185 (4.70)
0.025 (0.65) BSC
0.000 (0.00) 0.030 (0.76) 0.185 (4.70) PIN 1 INDENT
0.027 (0.70) 0.031 (0.80)
0.014 (0.35) 0.029 (0.75)
0.271 (6.90) 0.279 (7.10)
0.271 (6.90) 0.279 (7.10)
36
FN8148.0 March 18, 2005
X80000, X80001
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 37
FN8148.0 March 18, 2005

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